Laterizio: Difference between revisions

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Line 28: Line 28:
|1||MCLR|| ||MCLR
|1||MCLR|| ||MCLR
|-
|-
|2||I in|| ||AN0/VREF+/CN2/RA0
|2||Rx I in|| ||AN0/VREF+/CN2/RA0
|-
|-
|3||Q in|| ||AN1/VREF-/CN3/RA1  
|3||Rx Q in|| ||AN1/VREF-/CN3/RA1  
|-
|-
|4||Dati ICSP/GPIO2/PWM0/ANALOG0|| ||PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
|4||Dati ICSP|| ||PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
|-
|-
|5||Clock ICSP/GPIO3/PWM1/ANALOG1|| ||PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1  
|5||Clock ICSP|| ||PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1  
|-
|-
|6|||| ||AN4/C1IN-/RP2/CN6/RB2
|6||Tx Mic In|| ||AN4/C1IN-/RP2/CN6/RB2
|-
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|7|||| ||AN5/C1IN+/RP3/CN7/RB3  
|7|||| ||AN5/C1IN+/RP3/CN7/RB3  
Line 70: Line 70:
|22|||| ||PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
|22|||| ||PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
|-
|-
|23||Q out +|| ||AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
|23||Tx Q out +|| ||AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
|-
|-
|24||Q out -|| ||AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
|24||Q out -|| ||AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
|-
|-
|25||I out +|| ||AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14
|25||Tx I out +|| ||AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14
|-
|-
|26||I out -|| ||AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15
|26||I out -|| ||AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15

Revision as of 19:45, 31 August 2016

mo/demodulatore ssb digitale

laterizio e' un modulatore e demodulatore per SSB a metodo weaver implementato su un DSP a basso consumo, per RTX radio portatili

In ricezione, i segnali complessi I e Q vengono campionati simultaneamente su due ADC con risoluzione di 10bit e frequenza di 20Khz, filtrati con un filtro FIR, e moltiplicati con un oscillatore numerico in quadratura. I due segnali vengono poi sommati o sottratti a seconda della banda laterale desiderata.

uC

http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en532298 dsPIC33FJ128GP802

  • RAM: 16K
  • Flash: 128K
  • Timers: 5
  • UART: 2
  • primitive DSP
  • ADC 10/12bit
  • DAC 16bit

Mappa pin

Pin Funzione Nome porta sul uC
1 MCLR MCLR
2 Rx I in AN0/VREF+/CN2/RA0
3 Rx Q in AN1/VREF-/CN3/RA1
4 Dati ICSP PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
5 Clock ICSP PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1
6 Tx Mic In AN4/C1IN-/RP2/CN6/RB2
7 AN5/C1IN+/RP3/CN7/RB3
8 V - VSS
9 OSC1/CLKI/CN30/RA2
10 OSC2/CLKO/CN29/PMA0/RA3
11 SOSCI/RP4(1)/CN1/PMBE/RB4
12 SOSCO/T1CK/CN0/PMA1/RA4
13 V + VDD
14 PGED3/ASDA1/RP5 /CN27/PMD7/RB5
15 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6
16 INT0/RP7(1)/CN23/PMD5/RB7
17 TCK/SCL1/RP8(1)/CN22/PMD4/RB8
18 TDO/SDA1/RP9(1)/CN21/PMD3/RB9
19 V - VSS
20 10 uF tantalio verso VSS VCAP
21 PTT In PGED2/TDI/RP10(1)/CN16/PMD2/RB10
22 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
23 Tx Q out + AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
24 Q out - AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
25 Tx I out + AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14
26 I out - AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15
27 V - analogico AVSS
28 V + analogico AVDD

possibili alternative:

Letture

Phasing method:

Weaver method: